A high performance LDMOS transistor, which can be utilized as a power field effect transistor (FET), will have low on-resistance, RON, and high breakdown voltage, BV. Current processes dictate that to lower on-resistance, it is necessary to increase doping of the drain side drift region. However, such an increase in the drain side drift region doping results in a reduction in breakdown voltage, which is not acceptable. Greater decoupling of the intrinsic limit to the on-resistance of the power FET for a given breakdown voltage is needed.